1. Field of the Invention
This invention pertains to a semiconductor device having a so-called LOC (Lead on Chip) structure.
The LOC structure is configured by connecting to an upper surface of a semiconductor chip, an inner lead of a lead frame using a bonding agent, i.e. by attaching the semiconductor chip and the lead frame, such that the tip of the inner lead of the lead frame is positioned on top of the element-formation surface of the semiconductor chip. The bonding pad of the semiconductor chip and the tip of the inner lead are wire-bonded and resin-sealed.
Adopting the LOC structure gives increased electrical advantages and enables a chip with a large size to be installed in a small relatively package.
Regarding the electrical advantages, it becomes possible to perform wire bonding of the inner lead (for example, a bus-bar-lead ) to be used as an electric power line or a ground line separately from the inner lead to be used for each circuit block such as a sense amplifier and input section 3. The result is as follows.
1. The AL (Aluminum) wiring in a chip can be shortened and speeded up. PA0 2. The layout design of each circuit block in a chip is facilitated, and thus a semiconductor device structure with an increased number of bits can be easily developed. PA0 3. Since the bus-bar-lead is used for wiring, the resistance of the AL wiring can be decreased thereby enabling a semiconductor device suitable for high-speed operation to be provided. PA0 4. Since the number of bonding wires can be freely selected, it becomes possible to decrease the noise caused during operation of the sense amplifier for reading out data.
The LOC structure is also advantageous in that it can be inserted in a package with a predetermined size. Namely, the conventional package structure requires a large space for the wiring leads around a semiconductor chip but in contrast, the LOC structure can increase the ratio of the area of the chip to that of the package.
2. Description of the Related Arts
FIG. 1 is a slant view of a semiconductor device having a conventional LOC structure.
FIG. 2 shows an A--A cutaway of the semiconductor device having the conventional LOC structure shown in FIG. 1.
In FIGS. 1 and 2, 1 is a semiconductor chip (an LSI chip), 2 is an element-formation surface for the semiconductor chip 1, 3 is a lead frame, 4 is an inner lead of the lead frame 3, 5 is an outer lead of the lead frame 3, 6 is a double-sided adhesive tape for attaching the semiconductor chip 1 to the lead frame 3.
Also, 7 is the bus bar around the inner leads for a Vcc power source, 8 is the bus bar around the inner leads for a Vss power source, 9 is a bonding wire comprised of an Au wire, and 10 is a molding resin.
Such LOC structured semiconductor devices have been developed mainly as a technique for packaging DRAMs (Dynamic Random Access Memory) with capacities between four megabits [4 M] and sixteen megabits [16 M] for example, at the present and SRAMs (Static Random Access Memory) of four megabits [4 M ], for example, at the present. It removes from the conventional lead frame a part called a die-pad for loading a semiconductor chip and has an inner lead extended on to the element-formation surface of the semiconductor chip.
Also, the semiconductor device shown in FIG. 1 has the bus bars 7 and 8 with low impedances comprising iron, for example, in lieu of an aluminum power source wiring formed on a conventional semiconductor chip, which are treated as wirings to be wire-bonded to peripheral circuits at multiple places, thereby improving the electrical characteristics of a power source.
FIG. 3 shows a portion of a DRAM with a conventional LOC structure. FIG. 4 shows an equivalent circuit for the portion shown in FIG. 3 and represents a circuit diagram for an output stage of the semiconductor device having the conventional LOC structure shown in FIG. 1. FIG. 4 highlights the problems with the conventional structure. FIG. 5 shows a schematic plan view of the portion shown in FIG. 3 and represents a plan view of a semiconductor device having the conventional LOC structure shown in FIG. 1. FIG. 5 highlights a problem with the conventional structure.
With the recent trend of increasing the number of bits in a DRAM, multiple output buffers 11 loaded on a semiconductor chip has increased from eight [8], to sixteen [16], to thirty-two [32], . . . .
In FIG. 4, 12 and 13 are inverters, 14 and 15 are nMOS transistors, 16 is a bonding pad, 17 is an external lead, and 18 is an external load. R1 through R3, L1, and C1 through C4 are respectively resistances, an inductance, and capacitances of the parasitic impedance to the signal path from the bonding pad 16 to the external lead 17. The external load 18 is exemplified by a model, comprising a capacitance CL, resistances R4 and R5 and current sources J1 and J2.
As shown in FIG. 3, R1 represents the resistance of the bonding wiring 9. C1 is equal to half the total capacitance of the wire bonding 9 plus the parasitic capacitance between the bonding pad 16 and the final stage (comprising a buffer including nMOS 14 and 15) of the output buffer 11. C2 is equal to half the capacitance of the wire bonding 9 and half the total capacitance of the inner lead 4. C3 is equal to half the total capacitance of the inner lead plus half the total capacitance of the external lead 17. C4 is half the total capacitance of the external lead 17. CL is the total capacitance of the external load 18. R2 is the resistance of the inner lead 4. R3 is the resistance of the external lead 5. L1 is the inductance of the line from an output buffer 11 of the final stage to the foremost end of external lead 17. Reference numeral 20 in FIG. 3 represents a block obtained by dividing a memory cell array.
An input signal comes to an input pad via leads 4A-4AA and a bonding wire 9, and then received by the inner circuit. For example, in FIG. 3, the input signal is received by a "ROW DECODER". In general, a receiver circuit for receiving an input signal is called an input buffer. In FIG. 3, the input buffer is included in "ROW DECODER", which is omitted from the FIG. 3.
Normally, as well known, an input buffer receives an input signal on a control electrode (for example, a gate terminal) of MOS transistor and the input signal is amplified for an inner circuit. In a case where an input signal is received by a voltage-driving type element, input impedance to a signal transmission path does not affect operational speed so much. Whereas, the output signal outputted from an output buffer 11 conducts slower if an impedance increases due to longer length of a transmission path (4BB-4B). As described hereinbefore, input impedance affects the operational speed of the device smaller than the output impedance does.
Since noise generated when the multiple (eight [8], sixteen [16], thirty-two [32], . . .) output buffers 11 simultaneously switch, cannot be borne by the power source line alone, an effective countermeasure for the noise has been sought.
The position of a bonding pad outputting a signal, and the length and area of an inner lead transmitting a signal, should be given more consideration in terms of the electrical characteristics than a bonding pad or an inner lead receiving a signal.
That is, it should be kept in mind that an inner lead and a bonding pad transmitting a signal need to be configured to minimize the parasitic impedance components, i.e. R1, R2, R3, L1, and C1 through C4, shown in FIG. 3 for the purpose of achieving high-speed access.
However, a semiconductor device having the conventional LOC structure shown in FIG. 1 such as the DRAM shown in FIG. 3 treats an inner lead and a bonding pad transmitting a signal in the same way as it treats an inner lead and a bonding pad for solely receiving a signal, such that the bonding pad outputting a signal is arrayed in the direction of the longer side and near the middle of the element-formation surface 2 of the semiconductor chip 1 as shown in FIG. 5. Moreover the tip 4BB of the inner lead 4B for outputting a signal is positioned on the top in the middle and in the direction of the longer side of the element-formation surface 2 of the semiconductor chip 1, as with the tip 4AA of the inner lead 4A for solely receiving a signal.
Accordingly, the values of parasitic impedance components, i.e. R1, R2, R3, L1, and C1 through C4, become large, thereby causing the problem of delaying signal transmission and inhibiting expeditious readout.
Also, a semiconductor device having the conventional LOC structure such as shown in FIG. 1 has its signal paths 19 formed with kinked lines as shown in FIG. 5, thereby preventing fast operation. In FIG. 5, 20 is a block split from a memory cell array, 4A is an inner lead for solely receiving a signal, 21A is a bonding pad for receiving a signal, 21B is a bonding pad for transmitting a signal, and 4B is an inner lead for transmitting a signal.